Semiconductor memory device including non-volatile transistor for

Abstract

A non-volatile random access memory device includes a plurality of memory cells, each of which has a bistable (flip-flop) circuit which acts as an ordinary random access memory cell and at least one non-volatile memory transistor. The bistable circuit has two output terminals (a true output terminal and a complementary output terminal). One of the two output terminals is coupled to a control electrode of the non-volatile memory transistor, and the other output terminal is coupled to the drain of the non-volatile memory transistor. The source of the non-volatile memory transistor is coupled to a driving voltage source (e.g. 5 V) via a switching gate which is turned on when a control signal is applied thereto. In a normal operation mode, a normal driving voltage (e.g. 5 V) is supplied to the bistable circuit. On the other hand, when data in the bistable circuit is to be sheltered in the non-volatile memory transistor, a high voltage (e.g. 20 V) is supplied to the bistable circuit, whereby the non-volatile memory transistor stores the data in the bistable circuit. When the data stored in the non-volatile memory transistor is to be returned to the bistable circuit, the switching gate is turned on in response to a control signal. Thus, the data in the non-volatile memory transistor is restored in the bistable circuit. These operations can be easily performed at high speed with simple hardware elements.