Gate shield structure for power mos device

Abstract

A VDMOS device comprises a semiconductor wafer having a major surface with a first conductivity type drain region thereat. An array of second conductivity type body regions, spaced from each other by distance D, is diffused into the drain region from the first surface. The body regions each include a relatively high conductivity supplementary body region and a first conductivity type source region diffused therein from within the first surface boundary thereof. The spacing between each source region and the drain region defines a channel region at the first surface. A source electrode contacts the source and body regions and an insulated gate electrode overlies each channel region. A gate bond pad, in direct contact with the gate electrode, overlies a second conductivity type gate shield region and is insulated therefrom. The gate shield region is contiguous with the drain region and is spaced from the neighboring channel regions by distance D. The gate shield region includes a plurality of contact areas proximate to the periphery thereof and a plurality of relatively low conductivity portions disposed between the contact areas and the drain region. The source electrode ohmically contacts these contact areas.