The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 25, 1986
Filed:
Jun. 18, 1984
Applicant:
Inventors:
Mark E Fitzpatrick, San Jose, CA (US);
Cyrus Y Tsui, San Jose, CA (US);
Andrew K Chan, Milpitas, CA (US);
Albert L Chan, San Jose, CA (US);
Assignee:
Monolithic Memories, Inc., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R / ;
U.S. Cl.
CPC ...
371 15 ; 371 21 ; 371 25 ; 324 / ;
Abstract
A field programmable array logic circuit is described wherein existing sensing circuitry is employed along with circuitry to enable every fuse location to be isolated, so that both a.c. and verification testing takes place under the same conditions, i.e. voltage levels and frequency, which occurs during normal operation of the programmed circuit.
Fitzpatrick, Mark. (1986). Programmable array logic circuit with testing and verification circuitry (U.S. Patent No. 4625311). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4625311
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile