The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 22, 1986

Filed:

Feb. 15, 1984
Applicant:
Inventors:

William E Dougherty, Jr, Poughkeepsie, NY (US);

Stuart E Greer, Shelburne, VT (US);

William J Nestork, Charlotte, VT (US);

William T Norris, Georgetown, TX (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
357 80 ; 357 68 ; 357 74 ; 361414 ;
Abstract

A substrate for packaging semiconductor chips is provided which is structured with conductors having opposite ends terminating in a mounting surface and intermediate portions extending beneath the surface. The ends of the conductors are arranged in repeating patterns longitudinally along the substrate separated by orthogonal strips free of conductor ends to allow for dense surface wiring. The repeating patterns are arranged to allow for chip mounting sites having sufficient spacing to allow for surface wiring. In this way chips in the same and repeat pattern can be connected by personalized surface wiring and preset substrate conductors.


Find Patent Forward Citations

Dougherty, Jr, William. (1986). Personalizable masterslice substrate for semiconductor chips (U.S. Patent No. 4602271). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4602271

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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