The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 1986

Filed:

Dec. 07, 1984
Applicant:
Inventors:

William W Lee, Fountain Valley, CA (US);

Gareth L Shaw, Fountain Valley, CA (US);

James W Clayton, deceased, late of Santa Ana, CA (US);

Denise Bachino, administrator, Santa Maria, CA (US);

Assignee:

Hughes Aircraft Company, Los Angeles, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
29590 ; 29589 ; 29591 ; 29578 ; 1566611 ; 357 71 ;
Abstract

Inter-layer electrical shorting between layers of conductors of an integrated circuit caused by 'hillocks' in the bottom layer is prevented by the use of a double layer photoresist coatings atop the insulating layer that separates the metal layers. The double layer photoresist insures that irregularities in the dielectric layer caused by hillocks in the underlying insulating layer do not cause a break in the photoresist and a subsequent undesired etching of a spurious 'via' through the dielectric layer.


Find Patent Forward Citations

Lee, William. (1986). Process for fabricating multi-level-metal integrated circuits at high (U.S. Patent No. 4592132). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4592132

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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