Fabrication methods for high performance lateral bipolar transistors

Abstract

The lateral transistor is described which has both its base width and the emitter region of the transistor minimized. This minimization of the elements of the lateral transistor gives high performance. The lateral transistor which may be typically PNP transistor is formed in a monocrystalline semiconductor body having a buried N+ region within the body. A P type emitter region is located in the body. An N type base region is located around the side periphery of the emitter region. A P type collector region is located in the body surrounding the periphery of the base region. A first P+ polycrystalline silicon layer acting as an emitter contact for the emitter region is in physical and electrical contact with the emitter region and acts as its electrical contact. A second P+ polycrystalline silicon layer is located on the surface of the body to make physical and electrical contact with the collector region. A vertical insulator layer on the edge of the second polycrystalline silicon layer isolates the two polycrystalline silicon layers from one another. The N base region at its surface is located underneath the width of the vertical insulator layer. An N+ reach-through region extending from the surface of the body to the buried N+ region acts as an electrical contact through the N+ region layer to the base region. The width of the vertical insulator has a width which is equal to the desired base width of the lateral PNP transistor plus lateral diffusions of the collector and emitter junctions of the lateral PNP. The preferred structure is to have the emitter formed around the periphery of a channel or groove which has at its base an insulating layer such as silicon dioxide. The parasitic transistor is almost totally eliminated by this buried oxide isolation.