The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 25, 1986

Filed:

Dec. 13, 1984
Applicant:
Inventor:

Tadashi Shibata, Yokohama, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
2957 / ; 2957 / ; 29580 ; 29571 ; 148D / ; 148D / ; 148D / ; 357 51 ;
Abstract

A method of manufacturing a semiconductor memory device having a trench memory capacitor. First masks are formed on an element forming region of a semiconductor substrate formed of the element forming region and an element isolation region. A film formed of a different material from that of the first masks is deposited and is etched by anisotropic dry etching to leave second masks around the first mask. The semiconductor substrate is selectively etched using the first and second masks as an etching mask so as to form a first groove in the element isolation region. An insulation film is buried in the first groove. A portion of the first mask, formed at least above memory capacitor forming regions in the element forming region, is removed by etching, thereby forming a third mask on a portion excluding the memory capacitor forming region. The semiconductor substrate is selectively etched by using the second and third masks and the insulation film buried in the first groove as an etching mask so as to form second grooves in the respective memory capacitor forming regions. A distance between the first and second grooves is defined by the second masks in a self-alignment manner. A capacitor electrode is formed in the second grooves through a gate insulation film.


Find Patent Forward Citations

Shibata, Tadashi. (1986). Method of manufacturing semiconductor memory device having trench memory (U.S. Patent No. 4577395). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4577395

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…