The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 1986

Filed:

May. 09, 1984
Applicant:
Inventors:

David A Baglee, Houston, TX (US);

Michael C Smayling, Houston, TX (US);

Michael P Duane, Houston, TX (US);

Mamoru Itoh, Ibaragi, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
29571 ; 2957 / ; 2957 / ; 148-15 ; 148187 ;
Abstract

A method of making MOS integrated circuits employs high-pressure oxidation of the surface of a silicon slice to create thermal field oxide for device isolation. The implant used prior to this oxidation to provide the channel-stop regions beneath the field oxide may be at a lower dosage, and yet the field-transistor threshold voltage is maintained at a high level. Thus, encroachment of the channel stop impurity into the transistor channel is minimized, and higher density devices are permitted.


Find Patent Forward Citations

Baglee, David. (1986). Method of making integrated circuit with reduced narrow-width effect (U.S. Patent No. 4569117). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4569117

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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