The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 1985

Filed:

Jul. 19, 1982
Applicant:
Inventors:

Steven R Sutton, Beaverton, OR (US);

Michael S Hagen, Vancouver, WA (US);

David D Chapman, Portland, OR (US);

Glenn S Gombert, Hillsboro, OR (US);

Steven R Palmquist, Beaverton, OR (US);

Assignee:

Tektronix, Inc., Beaverton, OR (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L / ;
U.S. Cl.
CPC ...
375 10 ; 364551 ; 364569 ;
Abstract

An input apparatus for a multi-channel device, such as a logic analyzer, is disclosed, the input apparatus providing the multi-channel device with a programmable set-up and hold feature. The multi-channel device acquires a logic signal from a product under test, the logic signal having associated therewith an actual set-up and hold time with respect to an external clock signal. The actual set-up and hold times are entered into the multi-channel device via a keyboard and a display. The device has stored therein a desired set-up and hold time required by the logic signal relative to the external clock signal. In accordance with the actual and the desired set-up and hold times, the multi-channel device changes the relative orientation of the acquired logic signal with respect to the external clock signal, along the time axis until the set-up and hold times of the acquired logic signal are changed from the actual value to the desired value. As a result, the multi-channel device can be used to troubleshoot any product under test regardless of the set-up and hold times of the generated logic signals, relative to an external clock signal, associated therewith.


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