The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 10, 1985
Filed:
May. 03, 1983
John J Ennis, Corona, CA (US);
Robert K Booher, Temecula, CA (US);
Abstract
An FET complementary pair provides the output to a data line. A data input line is coupled to the gate of the P-FET via an OR gate configuration, and to the gate of the N-FET via an AND gate configuration. The output of each gate configuration is cross-connected to an input of the other. When the input data state changes, the two gate configurations provide delays which are effectively in tandem, so that the FET which was ON is first turned OFF, and after a short delay the other is turned ON. This delay ensures that both FET's are not ON at the same time, which prevents an undesirable power flow. To provide a high impedance 'float' state, an enable input and its complement are connected to the AND and OR gate configurations respectively.