The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 25, 1985
Filed:
Jun. 05, 1984
Siemens Aktiengesellschaft, Berlin & Munich, DE;
Abstract
A method for manufacturing VLSI complementary MOS field effect transistor circuits (CMOS circuits). By use of a suitable gate material, preferably a gate material comprised of silicides of high melting point metals, a threshold voltage of n-channel and p-channel CMOS-FETs having gate oxide thicknesses d.sub.GOX in a range of 10 to 30 nm is simultaneously symmetrically set by means of a single channel ion implantation. Given employment of tantalum silicide, the gate oxide thickness d.sub.GOX is set to 20 nm and the channel implantation is executed with a boron dosage of 3.times.10.sup.11 cm.sup.-2 and an energy of 25 keV. In addition to achieving a high low-level break down voltage for short channel lengths, this enables the elimination of a photolithographic mask. This represents an improvement with respect to yield and costs. The method serves for the manufacture of analog and digital CMOS circuits in VLSI technology.