The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 22, 1985

Filed:

Nov. 07, 1983
Applicant:
Inventors:

George F Anderson, Tempe, AZ (US);

Dan L Burt, Phoenix, AZ (US);

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
427 89 ; 427 90 ; 427102 ; 427103 ;
Abstract

Semiconductor devices with resistor regions, capable of operating at higher temperatures, and having improved bond pull strength are obtained by using a single layer (e.g. Ni--Cr) to act as a combined resistive layer and barrier layer. When placed in the contact windows between the semiconductor (e.g. Si) and the interconnect metallization, (e.g. Al) and Ni--Cr layer acts as a diffusion barrier to prevent interdiffusion of silicon and aluminum and contact alloying punch-through. When placed elsewhere on the device the Ni--Cr layer also serves as thin film resistor material. Wire bond pull strength is improved by placing an adhesion layer (e.g. polysilicon) beneath the portion of the resistive barrier layer underlying the bonding pads. The polysilicon layer rests on the insulator (e.g. SiO.sub.2) covering the semiconductor substrate.


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