The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 25, 1984
Filed:
Sep. 28, 1982
Junji Sakurai, Tokyo, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
At present, the majority of semiconductor devices are two-dimensional large-scale integration (LSI) semiconductor devices in which the semiconductor elements are arranged in a semiconductor layer in a two-dimensional manner. An aim of the techniques of production of semiconductor devices is to achieve, in the future, a super high integration amounting to 16 M bits or more per chip. For attaining such a super high integration, a multilayer semiconductor device must be produced. A method for producing a three-dimensional LSI semiconductor device prevents wasteful formation of semiconductor layers and insulating films. The method includes the step of forming, in a first semiconductor layer, a monitoring device for evaluating the circuit function of the semiconductor elements in the first semiconductor layer and subsequently forming another semiconductor layer above the first semiconductor layer. A preferred embodiment also includes the steps of: forming the impurity regions of the semiconductor elements by ion implantation; activating the implanted impurity ions by energy beam irradiation; and forming the insulating material regions of the semiconductor elements by high-pressure oxidation, or by low-temperature sputtering.