The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 23, 1984
Filed:
Jul. 12, 1982
Applicant:
Inventor:
Gordon C Godejahn, Jr, Santa Ana, CA (US);
Assignee:
Rockwell International Corporation, El Segundo, CA (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
29571 ; 2957 / ; 29578 ; 29591 ; 148187 ; 148188 ; 156643 ; 156653 ; 156657 ; 357 23 ; 357 41 ; 357 45 ; 357 59 ;
Abstract
A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices. The use of materials in successive layers having different etch characteristics permits selective oxidation of desired portions only of the structure without need for masking and removal of selected material from desired locations by batch removal processes again without use of masking. There results VLSI circuits having increased density and reliability.
Quick Actions:
Godejahn, Jr, Gordon. (1984). Process for and structure of high density vlsi circuits, having (U.S. Patent No. 4477962). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4477962
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile