The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 18, 1984
Filed:
Dec. 23, 1983
Eliezer Kinsbron, Highland Park, NJ (US);
William T Lynch, Summit, NJ (US);
AT&T Bell Laboratories, Murray Hill, NJ (US);
Abstract
An overall method for manufacturing an IGFET device having extremely shallow source and drain regions and reduced gate to source and drain overlap capacitances is disclosed. For silicon MOS devices, the method also provides for the formation of metal silicide layers on polysilicon gate electrodes and interconnection paths and the source and drain regions in the same fabrication step. Source and drain regions are formed by oxidation of an arsenic doped polysilicon source layer formed to be in contact with areas in the silicon surface in which such regions are to be formed. The rate of oxidation of the source layer exceeds the rate at which arsenic diffuses in the silicon at the oxidation temperature. Owing to a high segregation coefficient of arsenic in silicon dioxide, nearly all of the arsenic in the source layer is driven into extremely shallow source and drain regions which acquire high surface concentrations.