The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 04, 1984
Filed:
Mar. 22, 1982
Toshitaka Fukushima, Yokohama, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
In semiconductor devices, the transistors are isolated by means of either a PN junction isolation method or a passive isolation (PI) method. The present invention aims to improve the PI method, which is disadvantageous in that an electrode, electrically connected to the semiconductor substrate, causes a decrease in the integration density of the IC chip. In the present invention, the vacant space outside the element-forming regions is used to form the electrode and the integration density is not decreased due to the formation of the electrode. Since a polycrystalline silicon layer is in a groove formed in the vacant space, ohmic contact between the polycrystalline semiconductor material in the layer and the semiconductor substrate can be achieved while at the same time keeping the diffusion length of the impurities diffused from the polycrystalline silicon layer and the semiconductor substrate, very short. Therefore, upward diffusion of the impurities from the N.sup.+ -type buried layer can be effectively suppressed to realize a high breakdown voltage of the semiconductor devices.