Sub-micrometer channel length field effect transistor process

Abstract

A method for fabricating a semiconductor integrated circuit structure having a sub-micrometer length device element is described wherein a surface isolation pattern is formed in a semiconductor substrate which isolates regions of the semiconductor within the substrate from one another. These semiconductor regions are designated to contain devices. At least one layer is formed over the device designated regions and etched to result in a patterned layer having substantially vertical sidewalls some of which sidewalls extend across certain of the device regions. A controlled sub-micrometer thickness sidewall layer is formed on these vertical sidewalls. The patterned layer is then removed which leaves the pattern of sub-micrometer thickness sidewall layer portions of which extend across certain of the device regions. The desired pattern of PN junctions are now formed in the substrate using for example diffusion or ion implantation techniques with the controlled thickness sub-micrometer layer used as a mask. The effect is the transfer of the submicron pattern into underlying region. This method is particularly useful in forming a sub-micrometer length gate electrode of a field effect transistor.