The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 24, 1984
Filed:
Oct. 21, 1981
Applicant:
Inventor:
William W Lee, Fountain Valley, CA (US);
Assignee:
Hughes Aircraft Company, El Segundo, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
29571 ; 2957 / ; 29579 ; 29580 ; 148187 ;
Abstract
A process of fabricating high density CMOS integrated circuits having conductively interconnected wells. The conductive interconnection is provided by a buried conductor formed in combination with channel stops encircling each of the wells and prior to the fabrication of FET active devices at the surface of the wells. The channel stops, as provided by the process, are automatically aligned with and spaced apart from the source and drain regions of their respective FETs.
Lee, William. (1984). Method of fabricating high density high breakdown voltage cmos devices (U.S. Patent No. 4426766). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4426766
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile