Non-volatile programmable integrated semiconductor memory cell

Abstract

A non-volatile programmable integrated semi-conductor cell comprises a semiconductive substrate of one conductivity type, a reading insulated-gate field effect transistor partially incorporated in said substrate and having an insulated gate at the active surface of the substrate, and a floating gate electrode juxtaposed with and extending beyond the boundaries of the insulated gate, a pair of programming electrodes constituted by planar regions of the other conductivity type in the substrate, including a writing electrode and an erasing electrode each having an insulated gate of a thickness permitting junction crossing by hot carriers in partial overlap with floating gate electrode for capacitative coupling thereto, the region of overlap at said writing electrode being larger than that at said erasing electrode, and a diffusion region of the one conductivity type in said substrate next to and at a small distance from said writing electrode and having a surface area smaller than that of said writing electrode, at least partially, juxtaposed with the floating gate. The reading and writing electrodes may be integral with the source and drain regions of the reading field effect transistor.