The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 1983

Filed:

Nov. 18, 1982
Applicant:
Inventors:

Hormazdyzr D Dalal, Wappingers Falls, NY (US);

Bisweswar Patnaik, Wappingers Falls, NY (US);

Homi G Sarkary, Hopewell Junction, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B05D / ;
U.S. Cl.
CPC ...
430312 ; 430318 ; 430323 ; 156646 ; 1566591 ; 1566611 ; 156664 ; 156665 ; 156666 ; 156668 ; 2041 / ;
Abstract

A method for forming feedthrough connections, or via studs, between levels of metallization which are typically formed atop semiconductor substrates. A conductive pattern is formed which includes the first level metallurgy, an etch barrier and the feedthrough metallurgy in the desired first level metallurgical configuration. The via stud metallurgy alone is then patterned, preferably by reactive ion etching, using the etch barrier to prevent etching of the first level metallurgy. An insulator is then deposited around the via studs to form a planar layer of studs and insulator, after which a second level of metallization may be deposited.


Find Patent Forward Citations

Dalal, Hormazdyzr. (1983). Forming interconnections for multilevel interconnection metallurgy (U.S. Patent No. 4410622). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4410622

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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