The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 05, 1983
Filed:
Aug. 27, 1981
Hyman J Levinstein, Berkeley Heights, NJ (US);
Shyam P Murarka, New Providence, NJ (US);
Ashok K Sinha, New Providence, NJ (US);
Bell Telephone Laboratories, Incorporated, Murray Hill, NJ (US);
Abstract
In order to form MOSFET structures, a cobalt layer (16) is deposited and sintered, at about 400.degree. C. to 500.degree. C., on a patterned semiconductor wafer having exposed polycrystalline (14) or monocrystalline (11) silicon portions, as well as exposed oxide (15 or 25) portions. The cobalt reacts with exposed surfaces of the silicon portions and forms thereat such compounds as cobalt monosilicide (CoSi) or di-cobalt silicide (C0.sub.2 Si), or a mixture of both. The unreacted cobalt is selectively removed, as by selective etching in a suitable acid bath. A heat treatment at about 700.degree. C. or more, preferably in an oxidizing ambient which contains typically about 2 percent oxygen, converts the cobalt compound(s) into relatively stable cobalt disilicide (CoSi.sub.2). Subsequently, deposition of an in situ doped layer (33) of polycrystalline silicon (polysilicon) on the cobalt disilicide contacting the monocrystalline silicon portions--followed by gettering, deposition of a layer (34) of aluminum, and standard etch-patterning of the aluminum and polysilicon layers--completes the metallization of the desired MOSFET structures on the silicon wafer.