The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 24, 1982

Filed:

Jun. 30, 1980
Applicant:
Inventors:

Rahul Sud, Colorado Springs, CO (US);

Kim C Hardee, Manitou Springs, CO (US);

John O Heightley, Monument, CO (US);

Assignee:

INMOS Corporation, Colorado Springs, CO (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ; G11C / ; G11C / ;
U.S. Cl.
CPC ...
365200 ; 371 10 ;
Abstract

A redundancy scheme is described for use with an MOS memory having a main array of memory cells, and a plurality of spare memory cells. Typically, each memory cell is tested for operability by a conventional probe test. When a defective memory cell is found, an on-chip address controller responds to the probe test finding a defective cell by permanently storing and rendering continuously available a fully asynchronous electrical indication of the address of the defective cell. The address controller compares its stored data with memory cell information received during normal memory operation, and generates a control signal indicative of the receipt of an address which corresponds to a defective cell. A spare cell selector responds to the control signal by electrically accessing a spare memory cell and by prohibiting access of the defective memory cell.


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