The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 06, 1982
Filed:
Jun. 29, 1979
George C Feth, Yorktown Heights, NY (US);
Tak H Ning, Yorktown Heights, NY (US);
Denny D Tang, Yorktown Heights, NY (US);
Siegfried K Wiedmann, Peekskill, NY (US);
Hwa N Yu, Yorktown Heights, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A semiconductor circuit in which a plurality of transistors is provided, the collector regions/contacts and the base regions/contacts of the transistors being mutually self-aligned. In one embodiment, the collectors have conductive layer contacts (such as metal) and are self-aligned to polysilicon base contacts while in another embodiment the base contacts are comprised of a conductive (metal) layer while polysilicon is used for the collector contacts. The collectors of these transistors can be butted to a field oxide to reduce the extrinsic base area and to minimize excess charge storage in the base region. The base contacts, whether polysilicon or metal, etc. provide alternate base current paths so that the removal of the extrinsic base area does not adversely affect the total amount of base current which can flow. The use of a polysilicon layer for the base contacts, where 'fingers' are provided by the polysilicon layer, enhances wirability and the mode of fabrication of the structure, since the polysilicon fingers can have an insulating layer (grown oxide) thereover to provide electrical isolation from over-lying conductors. These self-alignment techniques provide enhanced electrical properties since the distance between the base and collector contacts is minimized and since the base-emitter depletion layer capacitance, the stored charge and the base series resistance are reduced. From a processing standpoint, an additional masking step is not required to form the collector regions.