Method of manufacturing an insulated gate field-effect transistor

Abstract

A method of manufacturing a device in a wafer with a P-type semiconductor, includes forming on a surface of the semiconductor body a layer of silicon dioxide doped with an N-type dopant. The portion of the doped silicon dioxide covering the interconnect work site area is removed and a masking layer of an oxidation impervious medium is formed over the wafer and thereafter removed from the field areas, as is the doped silicon dioxide layer. A thin layer of gate oxide is formed over the field areas. A layer of conductive polysilicon is formed over the entire wafer followed by a layer of oxygen impervious masking medium. The conductive polysilicon and masking medium layers are removed from all areas of the wafer except those whereat transistors are to be formed. The wafer is exposed to an oxidizing environment under an elevated temperature producing a field oxide over the exposed gate oxide. The elevated temperature of this operation drives the dopant in the doped silicon oxide layer into the semiconductor body forming doped source/drain regions and doped first level conductor runs. Thereafter the masking medium covering the interconnect work site area is removed and the work site area diffused with an N-type dopant. Finally, second level conductor runs are formed on the wafer.