Insulated gate field effect transistor

Abstract

An Insulated Gate Field Effect Transistor (IG FET) comprises two depletion mode gate portions formed along the surface of a V-shaped recess in a semiconductor layer, an enhancement mode gate portion disposed between the two depletion mode gate portions, and a source region and a drain region disposed on respective sides of, and adjacent to, the depletion mode gate portion at the surface of the semiconductor layer. The V-shaped recess extends downwardly from the surface of, and through, a first semiconductor layer having comparatively low impurity concentration into an underlying second semiconductor layer having comparatively high impurity concentration. The first semiconductor layer provides, in the recess, the depletion mode gate portion, and the second semiconductor layer provides, in the recess, the enhancement mode gate portion of the IG FET. The source region and drain region are disposed on respective sides of, and adjacent to, the V-shaped recess, and are spaced apart from each other at the uppermost surface of the substrate. The IG FET, as thus described, has a very short effective channel length, but also allows easy formation of electrodes on the source and drain regions. Moreover, the described IG FET is characterized by a high punch-through voltage regardless of the polarity of the voltage applied thereto, and precludes occurrence of the short-channel effect by virtue of the provision of the two depletion mode channels adjacent to the source region and drain region, respectively. A further embodiment employing dual recesses is also disclosed.