Logic circuit comprising circuits for producing a faster and a slower

Abstract

A logic circuit comprises a first and a second inverter for producing a first and a second inverted signal, respectively, one of which varies faster with a common variable input signal than the other. Responsive to the first inverted signal, a first buffer circuit produces a first output signal having a phase opposite to the input signal. Supplied with the second inverted signal, a second buffer circuit produces a second output signal having a phase same as the input signal. Preferably, the first buffer circuit comprises a depletion field effect transistor controlled by the first inverted signal and an enhancement field effect transistor controlled by the input signal. The second buffer circuit comprises an enhancement field effect transistor controlled by the second inverted signal and a depletion field effect transistor controlled by the input signal. More preferably, each of the first and the second inverters comprises a driving and a load field effect transistor. Amplification characteristics are rendered different from each other between the driving transistors of the first and the second inverters and/or between the load transistors of the respective inverters so as to make the first inverted signal have a level higher than the second inverted signal within an interval of time during the variation of the input signal.