The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 1981
Filed:
Aug. 13, 1979
Sumit Dasgupta, Wappingers Falls, NY (US);
Prabhakar Goel, Poughkeepsie, NY (US);
Thomas W Williams, Longmont, CO (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
One of the significant features of the invention, as in U.S. Pat. No. 3,783,254, is the implementation of shift register latches as basic building blocks in a logic organization and system with combinational logic networks which provide the excitation for the shift register latches. These shift register latches in the invention as well as in the patent contain a pair of latches where one is a 'master' latch and another a 'slave'. The structure in the patent requires the 'master' and 'slave' latches to be part of the shift register for scan-in/scan-out. However, only the 'master' may be set with data from the logic system surrounding it while the 'slave' may only be set with data which previously resided in the related 'master' latch. Thus, in those logic organizations where only the 'master' latch output is required, the usefulness of the 'slave' latch is limited to scan-in/scan-out. In the shift register latch of the invention, the 'slave' latch must be set with the data that resided in the related 'master' latch during scan-in/scan-out. However, in logic systems requiring the use of only one latch of the shift register latch, both 'master' and 'slave' latches can perform independent of the other; that is, each latch may be set with data from the logic system without any influence from the other latch in the same shift register latch. Similarly, both 'master' and 'slave' may feed different sections of the logic surrounding it.