The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 1981

Filed:

May. 26, 1978
Applicant:
Inventors:

Tokumasa Yasui, Kodaira, JP;

Minoru Fukuda, Kodaira, JP;

Tatsumi Shirasu, Tokyo, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B01J / ;
U.S. Cl.
CPC ...
29571 ; 2957 / ; 29578 ; 148187 ; 357 59 ; 357 91 ;
Abstract

An offset gate MIS device is fabricated by forming an insulating film with a gate insulator portion as a part thereof on the surface of a semiconductor substrate having one conductivity type, providing a gate electrode on a portion of the insulating film, using the gate electrode as a mask to apply impurities of the other conductivity type with a first impurity concentration to the surface of the semiconductor substrate through the insulating film, forming a shielding film on the surface of that portion of the insulating film which is near the gate insulator portion beneath the gate electrode, using the shielding film as a mask to remove an unmasked portion of the insulating film so as to selectively expose the surface of the semiconductor substrate, applying impurities of the other conductivity type with a second impurity concentration higher than the first impurity concentration to the exposed surface of the semiconductor substrate, and heating the resultant structure to diffuse the impurities into the semiconductor substrate to form source and drain regions therein.


Find Patent Forward Citations

Yasui, Tokumasa. (1981). Method for fabrication of offset gate mis device (U.S. Patent No. 4258465). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4258465

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…