The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 06, 1981
Filed:
Oct. 30, 1978
Applicant:
Inventors:
Kenji Natori, Kamakura, JP;
Fujio Masuoka, Yokohama, JP;
Assignee:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
357 23 ; 357 22 ; 357 55 ; 357 56 ; 357 58 ; 357 90 ;
Abstract
The first and second intrinsic semiconductor layers of thickness d are formed on a P type semiconductor substrate, keeping a prescribed interval therebetween, whereby a groove of depth d may be made between these layers. A dielectric layer is formed in such a way that it may cover a base and sides of the groove and a surface of the intrinsic semiconductor layer. On this surface, a gate electrode formed of polysilicon exists. Diffusion regions of a source and a drain of depths X.sub.sj and X.sub.dj are formed, in the neighborhood of groove sides, in the first and second intrinsic semiconductor layers (X.sub.sj, X.sub.dj d), resulting in an MOS transistor.