The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 30, 1980

Filed:

Mar. 08, 1979
Applicant:
Inventor:

Robert C Dobkin, Hillsborough, CA (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
357 51 ; 357 13 ; 357 45 ; 357 86 ;
Abstract

In a monolithic integrated circuit, on-chip trimming is implemented by connecting a zener diode across each element of a plural element trimmable resistor. Adjacent diodes are connected back to back and a pair of conventional bonding pads connected thereto. In trimming, when it is desired to short out one of the trimmable elements, the associated diode is subjected to an overload pulse by means of test probes applied to the bonding pads. Since the diodes are connected back to back, the pulse polarity will determine which diode is overloaded in the reverse bias condition. Thus, the trimmable element to be shorted is determined by pulse polarity and only one bonding pad is needed for each pair of trimmable elements.


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