The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 15, 1980
Filed:
Nov. 20, 1978
Applicant:
Inventor:
Ronald W Brower, Dayton, OH (US);
Assignee:
NCR Corporation, Dayton, OH (US);
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; B01J / ; H01L / ;
U.S. Cl.
CPC ...
148-15 ; 29571 ; 148187 ; 357 23 ; 357 41 ; 357 59 ; 357 91 ;
Abstract
A process for forming a CIS (conductor-insulator-semiconductor) integrated circuit having one or more field-effect memory transistors, and one or more polysilicon resistors and/or polysilicon conductors. The polysilicon components are formed to predetermined sizes, as needed, so that the implant used to establish the memory threshold voltage of the transistor also provides the desired polysilicon resistance value(s). The process may be used to simultaneously form both memory and non-memory transistors.
Brower, Ronald. (1980). Cisfet processing including simultaneous doping of silicon components (U.S. Patent No. 4212684). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4212684
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile