The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 01, 1980

Filed:

Nov. 20, 1978
Applicant:
Inventor:

Ronald W Brower, Dayton, OH (US);

Assignee:

NCR Corporation, Dayton, OH (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; B01J / ;
U.S. Cl.
CPC ...
148-15 ; 148187 ; 357 23 ; 357 40 ; 357 59 ; 357 91 ;
Abstract

A process for forming a CIS (conductor-insulator-semiconductor) integrated circuit having one or more non-memory field-effect transistors, and one or more polysilicon resistors and/or polysilicon conductors. A single mask and implant sequence is used to establish the threshold voltage of the field-effect transistor and the resistance (conductance) of the polysilicon components. The polysilicon components are formed to predetermined sizes, as needed, so that the threshold-determining implant provides the desired polysilicon resistance value(s).


Find Patent Forward Citations

Brower, Ronald. (1980). Cisfet processing including simultaneous implantation of spaced (U.S. Patent No. 4210465). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4210465

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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