The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 10, 1980
Filed:
Nov. 17, 1978
Applicant:
Inventor:
Jerry Mar, Sunnyvale, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365 95 ; 365154 ; 365185 ; 365228 ;
Abstract
A non-volatile MOS memory cell which includes a bistable (flip-flop) circuit with slightly imbalanced loads. An electrically programmable, floating gate device is coupled across a portion of one of the loads to permit selective shunting. When the cell is powered-down (such as at power failure), the floating gate is either charged or discharged as a function of the state of the flip-flop. When power is reapplied, the imbalance caused by the selective shunting forces the flip-flop to its previous state. The relatively small cell does not require resetting, and the stored information is returned in its true (non-complementary) form when the cell is reactivated.