The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 1980

Filed:

Nov. 20, 1978
Applicant:
Inventor:

Prabhakar Goel, Poughkeepsie, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
371 27 ; 324 / ; 371 23 ;
Abstract

A path oriented decision making test pattern generator is embodied in a logic chip test system for testing large-scale integrated circuits having many internal nodes inaccessible to the test probes of chip testing machines. For each designated possible chip fault, consisting of a stuck-high or stuck-low voltage at a node of the chip logic network, the generator provides a test pattern of signals to be applied to the input pins of each chip, so that the resulting signal at an output pin indicates whether the fault is present in the chip.


Find Patent Forward Citations

Goel, Prabhakar. (1980). Logic chip test system with path oriented decision making test pattern (U.S. Patent No. 4204633). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4204633

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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