Symmetrical cell layout for static ram

Abstract

A symmetrical structural layout for the principal components of each cell in a group of four mutually contiguous cells of an array of memory cells is disclosed. A common drain supply node is centrally disposed within the group and is coincident with the intersection of first and second mutually perpendicular axes of symmetry. Corresponding components of contiguous cells in each row and column are symmetrically disposed with respect to each of the first and second axes of symmetry. In a preferred embodiment, the principal components of each cell include a plurality of insulated gate field-effect transistors each having a source diffusion region and a drain diffusion region formed within the substrate and a plurality of impedance devices electrically connecting the common drain supply node to the drain diffusions of the transistors in each cell. The impedance devices extend radially from the common drain supply node into the interior of each cell, and at least one of the diffused regions of each transistor in each cell is formed in common with a diffused region of a transistor of a contiguous cell.