The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 14, 1978
Filed:
Oct. 04, 1976
Floyd O Arntz, Newton, MA (US);
Micro-Bit Corporation, Lexington, MA (US);
Abstract
A buried junction MOS memory capacitor target device for electron beam addressable READ/WRITE memories is described along with a method of using the same. The memory capacitor target structure comprises a planar semiconductor substrate of various degrees of complexity having a highly conducting coating providing a low resistance ohmic contact to the substrate backside and an N-type planar semiconductor overlayer forming with the substrate topside a bipolar detector junction. An insulating layer overlies the N-type layer and a conducting coating overlies the insulating layer. The device is employed with an electron beam of sufficient energy to penetrate the latter two layers and to produce carrier-pairs in the N-type overlayer. Electrical access to the device is provided by one contact to the substrate backside and one contact to the conducting coating overlying the insulator. Means are provided within the semiconducting portion of the device for limiting the electrostatic potential difference developed across the bipolar detector junction as a result of changes in the potentials applied to the electrical contacts. This may be achieved by fabricating the semiconducting portion of the device to provide for the occurrance of avalanche conduction within the detector junction whenever the reverse polarity potential difference across the junction exceeds a desired value. Alternatively the reach through effect commonly observed in thin base bipolar transistors when the collector-base potential difference exceeds a critical value can be employed to limit the reverse potential developed across the bipolar detector junction. This may be achieved by employing a planar semiconducting substrate comprised by a thin P-type layer overlying an N-type layer. In operation the design affords a means for applying the desired potential differences across the insulator for the various steps of memory operation and also affords a means for developing a desired reverse polarity potential difference across the buried bipolar detector junction for the duration of the read process.