The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 20, 1977

Filed:

Jan. 05, 1976
Applicant:
Inventor:

John A Bayliss, Sunnyvale, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G04C / ;
U.S. Cl.
CPC ...
58 2 / ; 58 395 ; 58 5 / ; 58 / ;
Abstract

A random access memory is combined with a programmable logic array to count time pulses within an integrated circuit watch. A master oscillator drives the internal timing clocks and serves as a time standard for a timing and control circuit means which manipulates data within the random access memory. The timing and control circuit may contain a programmable read-only memory so that words stored within the random access memory may be read, and manipulated, in a selected sequence. The programmable logic array increments the word selectively read from the random access memory, compares it to a limit value and generates one or more flags according to the desired data manipulation. Words stored within the random access memory may be selectively displayed by a liquid crystal display or light emitting diode display in a selected format determined by the programmable read-only memory. A driver circuit coupled to the display may also contain a read-only memory so that the data may be displayed in a selected one of plurality of display fonts. The operational and display modes may be customized by appropriately modifying the programmable logic array and read-only memories without altering the system architecture.


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