The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 08, 1977
Filed:
Feb. 13, 1976
Dale A Heuer, Stewartville, MN (US);
John F Roemer, Rochester, MN (US);
Michael J Sheehan, Rochester, MN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An FET read only memory array having bit locations arranged in rows and columns utilizes a dynamic array and static sensing. A dynamic first address selects the gate line of a selected column and a second address selects the source line or lines to select one or more bits within the selected column. The presence or absence of a gate at a selected bit location determines whether a first or second logic level is present at the sense or drain line serving the bit location. An additional column of FET bit positions each with a gate has the gate line activated toward the conclusion of the cycle to provide a path to ground for the elimination of any charge on a sense line in preparation for the next succeeding cycle. The sensed output from a selected bit location is latched until reset.