The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 23, 1977
Filed:
Jun. 17, 1976
Applicant:
Inventor:
Gregorio Spadea, Saratoga, CA (US);
Assignee:
National Semiconductor Corporation, Santa Clara, CA (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
B01J / ;
U.S. Cl.
CPC ...
29571 ; 29580 ; 357 42 ; 357 56 ;
Abstract
The method for fabrication of a self-aligned gate CMOS structure which employs no additional masking steps as compared to the standard CMOS fabrication process, this improved process providing the advantages of self-alignment between the N+ and P+ source and drain diffusions with respect to their gate regions, and metal contact openings which do not overlap the edges of the P+ or N+ source and drain regions. The self-aligning gate region is defined by a silicon nitride gate layer. Several embodiments of the novel process are described.