The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 05, 1977
Filed:
Aug. 25, 1975
Applicant:
Inventor:
Richard H Heeren, Palatine, IL (US);
Assignee:
Teletype Corporation, Skokie, IL (US);
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ; H03K / ; H03K / ;
U.S. Cl.
CPC ...
307269 ; 307205 ; 307208 ; 307265 ;
Abstract
A phased, four-output clock generator implemented on-chip with MOSFETs, has two phased inputs .phi..sub.A and .phi..sub.B thereto. If .phi..sub.A and .phi..sub.B are properly time-phased (in sequence: .phi..sub.A =1, .phi..sub.B =0; .phi..sub.A =0, .phi..sub.B =0; .phi..sub.A =0, .phi..sub.B =1; and .phi..sub.A =0, .phi..sub.B =0) the four outputs are time phased as:
Heeren, Richard. (1977). Logic circuits and on-chip four phase fet clock generator made therefrom (U.S. Patent No. 4034242). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4034242
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile