The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 07, 1977
Filed:
Jun. 21, 1976
Lawrence Griffith Heller, Brewster, NY (US);
Lewis Madison Terman, South Salem, NY (US);
Yen Sung Yee, White Plains, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
The voltages to be compared are applied to a passive MOS capacitor differencing circuit for producing a voltage difference signal, which then is amplified by a high-gain non-precision FET amplifier, the output of which is passed through a low output impedance FET buffer amplifier to a FET latching circuit. Capacitive coupling is used for enabling the amplifiers to be independently biased and to eliminate D.C. offsets. The operating cycle of the comparator has two periods. During an initial set-up or preconditioning period the amplifiers are self-biased by appropriate switching actions which cause each of the amplifiers to be set at a desired operating point that is maintained when its respective bias switching connection subsequently is opened. The bias switch openings in the respective amplifier and latching stages are timed to occur in a chosen sequence which causes the switching transients to be absorbed. At the end of the preconditioning period, the comparator is set up for operation in the comparison period during which the input signals are compared.