The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 29, 1977

Filed:

Sep. 02, 1975
Applicant:
Inventors:

Akihiro Tomozawa, Hinode, JA;

Takanori Nishimura, Kokubunji, JA;

Takashi Yamaguchi, Kodaira, JA;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
148187 ; 148 335 ; 148189 ; 357 34 ; 357 48 ;
Abstract

In order to prevent the formation of a parasitic PNPN thyristor in an integrated circuit having at least one NPN transistor, a layer of semiconductor material of a conductivity type opposite that of the substrate is formed on the substrate. An isolation region of the same conductivity type as the substrate is formed on this layer and a further layer of the same conductivity type as the isolation region, but of a higher impurity concentration, is formed on the back surface of the substrate. A diffusion layer of the same conductivity type as the substrate, which serves as the base region of the NPN transistor, is formed on the layer having the conductivity type opposite to that of the substrate. A further layer of the same conductivity type and a higher impurity concentration than the isolation region is formed on the back surface of the substrate and an insolation layer is formed on the back surface of the substrate and on the substrate. A further diffusion layer of a conductivity type opposite to that of the substrate, which serves as the emitter region of the transistor is formed using the insolation layer as a mask.


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