Upper bounds address checking system for providing storage protection

Abstract

Data processing circuitry for performing two serially related arithmetic operations during one and the same machine control cycle and employing an independent zone parallel type arithmetic unit capable of simultaneously performing independent arithmetic operations in the different zones thereof. Data transfer circuitry is provided for immediately supplying the output result of a first arithmetic unit zone back to the input of a second arithmetic unit zone for immediately producing a second and different result. Such transfer circuitry is constructed to operate in an asynchronous manner so that the first result is supplied back to the input of the second arithmetic unit zone as soon as it becomes available at the output of the first arithmetic zone. Thus, a second result, which is dependent on the first result, is produced during the same machine control cycle as the first result. This data processing circuitry is particularly useful for providing storage protection for a data processor. In such case, the current storage address and a requested storage access length value are supplied to the first arithmetic unit zone for producing a new address representing the upper extent of the storage access request. The resultant new address is immediately supplied back to the input of the second arithmetic unit zone for combining same with an upper limit address for immediately producing an upper bounds extent error when the new address exceeds the upper limit address.