The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 30, 1976

Filed:

Dec. 21, 1970
Applicant:
Inventors:

Edward F Duffek, Cupertino, CA (US);

Ernest J Funk, Cupertino, CA (US);

Alfred S Jankowski, San Jose, CA (US);

Jack C Lane, Saratoga, CA (US);

William L Lehner, Los Altos Hills, CA (US);

Floyd F Oliver, Los Altos, CA (US);

Mark R Schneider, San Jose, CA (US);

Assignee:

Signetics Corporation, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
357 70 ;
Abstract

Semiconductor devices containing integrated circuits are attached directly to external package leads by pressing simultaneously a plurality of groups of leads against bonding pads on a plurality of face-up semiconductor dice and heating the composite structures. Solder bumps on the bonding pads contain hard pedestals which prevent the overlying leads from being pushed into the faces of the semiconductor devices while the solder on the solder bumps melts to form the bonds between the leads and the underlying semiconductor dice. The process for carrying out this operation lowers significantly the cost of each packaged semiconductor device and the resulting structure is more reliable than structures of the prior art.


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