The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2026

Filed:

Mar. 12, 2024
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Vivek K Arora, San Jose, CA (US);

Woochan Kim, San Jose, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); H01F 27/28 (2006.01); H10W 40/25 (2026.01); H10W 70/40 (2026.01); H10W 72/00 (2026.01); H10W 74/01 (2026.01); H10W 74/10 (2026.01);
U.S. Cl.
CPC ...
H10W 90/811 (2026.01); H01F 27/2804 (2013.01); H10W 40/253 (2026.01); H10W 70/417 (2026.01); H10W 70/481 (2026.01); H10W 72/073 (2026.01); H10W 74/01 (2026.01); H10W 74/111 (2026.01); H01F 2027/2809 (2013.01); H10W 72/075 (2026.01); H10W 72/884 (2026.01); H10W 90/755 (2026.01); H10W 90/759 (2026.01);
Abstract

A power converter package includes a leadframe including first and second die pads, and supports connected to first leads, and second leads. A first semiconductor die including first bond pads is on the first die pad, and a second semiconductor die including second bond pads is on the second die pad. A transformer stack includes a top magnetic sheet and a bottom magnetic sheet on respective sides of a laminate substrate that includes a coil within, and coil contacts. A silicon block is attached to the bottom magnetic sheet and edges of the laminate substrate are attached to the supports. Bond wires are between the first bond pads and the second leads, the second bond pads and the second leads, and the first and second bond pads and the coil contacts. Mold encapsulates the respective semiconductor and the transformer stack. A bottom of the silicon block is exposed from the mold.


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Quick Actions:

Arora, Vivek. (2026). Isolated semiconductor package with hv isolator on block (U.S. Patent No. 12796577). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12796577

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