The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2026

Filed:

Sep. 30, 2023
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Ninad Shahane, San Francisco, CA (US);

Vivek Arora, San Jose, CA (US);

Kwang-Soo Kim, Sunnyvale, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10W 40/25 (2026.01); H10W 70/40 (2026.01); H10W 72/00 (2026.01); H10W 74/01 (2026.01); H10W 74/10 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 40/255 (2026.01); H10W 70/424 (2026.01); H10W 74/01 (2026.01); H10W 74/111 (2026.01); H10W 72/073 (2026.01); H10W 72/075 (2026.01); H10W 72/884 (2026.01); H10W 90/736 (2026.01); H10W 90/756 (2026.01);
Abstract

An example includes: a package substrate having a die pad with a device side surface and a thermal pad on an opposite side surface; a thermal dissipation structure mounted to the die pad, the thermal dissipation structure including a thermally conductive insulator core and thermal conductors on a device side surface and on a substrate mount surface opposite the device side surface; at least one semiconductor device die mounted to the device side surface of the thermal dissipation structure; electrical connections formed between leads on the package substrate and bond pads on the at least one semiconductor device die; and mold compound covering the electrical connections, the at least one semiconductor device, and portions of the package substrate, portions of the leads of the package substrate forming terminals, and the thermal pad exposed from the mold compound and forming a thermal pad for a semiconductor device package.


Find Patent Forward Citations

Quick Actions:

Shahane, Ninad. (2026). Semiconductor device package with integral thermal dissipation structure (U.S. Patent No. 12796466). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12796466

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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