The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2026

Filed:

May. 17, 2024
Applicant:

Ngk Insulators, Ltd., Nagoya-City, JP;

Inventor:

Ikuhisa Morioka, Handa, JP;

Assignee:

NGK INSULATORS, LTD., Nagoya, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10P 72/76 (2026.01); H01J 37/32 (2006.01); H10P 72/00 (2026.01); H10P 72/72 (2026.01);
U.S. Cl.
CPC ...
H10P 72/7616 (2026.01); H01J 37/32724 (2013.01); H10P 72/0432 (2026.01); H10P 72/0434 (2026.01); H10P 72/0602 (2026.01); H10P 72/722 (2026.01); H01J 2237/3321 (2013.01); H01J 2237/334 (2013.01);
Abstract

The wafer placement table includes a ceramic plate, a thermal diffusion plate, a first adhesive layer, a cooling plate, and a second adhesive layer. The ceramic plate has a wafer placement surface on its upper surface, and includes built-in electrodes. The thermal diffusion plate is provided on the lower surface of the ceramic plate. The first adhesive layer bonds the ceramic plate and the thermal diffusion plate together. The cooling plate is provided on the lower surface of the thermal diffusion plate, and internally includes a refrigerant flow path. The second adhesive layer is provided between the thermal diffusion plate and the cooling plate. The second adhesive layer is provided with an adhesive part and a hollow part, the adhesive part bonding the thermal diffusion plate and the cooling plate together, the hollow part being a gap provided between the thermal diffusion plate and the cooling plate.


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Morioka, Ikuhisa. (2026). Wafer placement table and method of using the same (U.S. Patent No. 12796397). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12796397

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