The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2026

Filed:

Dec. 01, 2023
Applicant:

Ebara Corporation, Tokyo, JP;

Inventor:

Kazuma Ideguchi, Tokyo, JP;

Assignee:

EBARA CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10P 72/00 (2026.01); H10P 74/00 (2026.01); H10P 14/46 (2026.01);
U.S. Cl.
CPC ...
H10P 72/0612 (2026.01); H10P 72/0604 (2026.01); H10P 74/232 (2026.01); H10P 14/46 (2026.01); H10P 72/0476 (2026.01);
Abstract

When a failure has occurred in a semiconductor manufacturing apparatus, lowering of throughput thereof is suppressed. A method for controlling operation of a semiconductor manufacturing apparatus, which comprises one or plural processing modules and each processing module comprises plural submodules, comprises steps for: judging whether a failure has occurred in at least one of the plural submodules; judging whether at least one submodule which is not in a failed state exists in a processing module to which the failed submodule belongs; obtaining throughput in a state that the one or plural processing modules are controlled to perform operation while the failed submodule is controlled to stop its operation; judging whether the throughput is larger than a predetermined threshold; and continuing operation of the one or plural processing modules while controlling the failed submodule to stop its operation, in the case that the throughput is larger than the predetermined threshold.


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Ideguchi, Kazuma. (2026). Semiconductor manufacturing apparatus and method for controlling operation of semiconductor manufacturing apparatus (U.S. Patent No. 12796380). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12796380

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