The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2026

Filed:

Aug. 30, 2023
Applicant:

Raytheon Company, Waltham, MA (US);

Inventors:

Paul A. Drake, Friday Harbor, WA (US);

Christopher Moshenrose, Encinitas, CA (US);

Heather D. Leifeste, Santa Barbara, CA (US);

Assignee:

RAYTHEON COMPANY, Waltham, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10F 39/00 (2025.01);
U.S. Cl.
CPC ...
H10F 39/809 (2025.01); H10F 39/018 (2025.01);
Abstract

A method of eliminating interconnect strains in a stack-up is provided. The method includes providing a detector portion including a detector substrate and detector layers, providing a read-out integrated circuit (ROIC) stack-up including ROIC layers and an initial ROIC substrate, removing the initial ROIC substrate from the ROIC layers, attaching a new ROIC substrate to a first surface of the ROIC layers, the new ROIC substrate having a coefficient of thermal expansion (CTE) that matches a CTE of the detector substrate and hybridizing the detector layers to a second surface of the ROIC layers by way of interconnects.


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Drake, Paul. (2026). Eliminating interconnect strains in microcircuits (U.S. Patent No. 12796147). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12796147

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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