The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2026

Filed:

May. 01, 2023
Applicant:

Semiconductor Components Industries, Llc, Scottsdale, AZ (US);

Inventors:

Swarnal Borthakur, Boise, ID (US);

Marc Allen Sulfridge, Boise, ID (US);

Jeffrey Peter Gambino, Gresham, OR (US);

Vladimir Korobov, San Mateo, CA (US);

Richard Mauritzson, Meridian, ID (US);

David T. Price, Gresham, OR (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10F 39/00 (2025.01); H10W 42/00 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10F 39/809 (2025.01); H10F 39/018 (2025.01); H10F 39/8053 (2025.01); H10F 39/8063 (2025.01); H10F 39/811 (2025.01); H10W 42/00 (2026.01); H10W 90/00 (2026.01);
Abstract

A semiconductor device may include a first chip that includes a first wafer and a first dielectric layer disposed thereon. The semiconductor device may include a second chip that includes a second wafer and a second dielectric layer disposed thereon, the second chip having a backside surface and a frontside surface opposed to the backside surface, the second chip being bonded to the first chip at the frontside surface to define a bond line between the first dielectric layer and the second dielectric layer. An opening through the backside surface of the second chip may extend into the second dielectric layer, and a bond pad may be disposed within the second dielectric layer between the second wafer and the bond line.


Find Patent Forward Citations

Quick Actions:

Borthakur, Swarnal. (2026). Chip stacking with bond pad above a bondline (U.S. Patent No. 12796146). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12796146

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